There are several integrated circuit logic families available from which to choose when designing an integrated circuit. ECL (emitter-coupled logic) is a type of integrated circuit logic which uses bipolar transistors. CMOS is another type of integrated circuit logic, however CMOS uses complementary MOSFET transistors. ECL circuits have the advantage of high speed, but they consume a large amount of power. CMOS logic circuits have the advantages of low power dissipation, high input resistance, low output resistance, and low noise generation. Combining ECL and CMOS on an integrated circuit therefore provides the important advantages of high speed and low power consumption. ECL is used in those circuit portions requiring higher processing speeds. CMOS is used to reduce power consumption in those circuit portions that are less time-critical.
ECL has short switching times because the swing between high and low logic states is only about one volt. In contrast, CMOS logic states may swing the full rail of the power supply voltage, or approximately 5 volts. Therefore, for integrated circuits utilizing both ECL and CMOS logic, converter circuitry must be provided internally on the integrated circuit for transitioning from ECL to CMOS logic levels.
A prior art level converter 10 is shown in FIG. 1. A pair of N-channel MOS transistors 12 and 13 is connected to form a current mirror. A power supply voltage is provided to supply the current mirror through a pair of P-channel MOS transistors 11 and 14. The gates of the P-channel MOS transistors 11 and 14 receive signals V.sub.I and V.sub.I, respectively. A CMOS logic signal labelled V.sub.OUT is provided on the mirror side of the current mirror at node 15.
Converter 10 provides signal V.sub.OUT at a CMOS logic high if V.sub.I is at a logic low (and V.sub.I is at a logic high), and provides signal V.sub.OUT at a logic low if V.sub.I is at a logic high (and V.sub.I is at a logic low). To output a logic high CMOS level, converter 10 receives signal V.sub.I which will be low enough below the threshold voltage (V.sub.T) to make the P-channel transistor 14 conductive. When the P-channel transistor 14 is conductive, V.sub.OUT is pulled high to V.sub.DD. V.sub.I will be high enough to cause the P-channel transistor 11 to become substantially non-conductive, which causes node 16 to be discharged through the N-channel transistor 12 to one N-channel V.sub.T, which is sufficient to make the N-channel transistor 13 substantially non-conductive. To output a logic low CMOS level, V.sub.I will be sufficiently below V.sub.T to make the P-channel transistor 11 conductive and V.sub.I will be sufficiently high to make the P-channel transistor 14 substantially non-conductive. N-channel transistors 12 and 13 are conductive, which causes V.sub.OUT to be pulled low to V.sub.SS. When transistor 11 is conductive, a current path is created through transistor 11 and transistors 12 causing a constant DC current to flow from V.sub.DD to V.sub.SS. This constant DC current is undesirable, but if only a few converters 10 are used on an integrated circuit, the small DC current may be insignificant. However, if a large number of converters 10 are required for a particular application, the total power consumed because of the DC current flow can become substantial.
An example of prior art circuit 10 is described in Pat. No. 4,961,011, issued on Oct. 2, 1990 to Ide et al.